Chip Design Technology Summit & IC Engineers' Carnival

Date: August 24, 2023

Venue: Conference Room 1, Hall 1, Shenzhen Convention and Exhibition Center (Futian)

Organizers: elexcon Shenzhen International Electronic Exhibition, EETOP Chip - Creation Network

Conference Agenda

09:00 - 9:20	Registration and Admission
09:20 - 9:30	Welcome Remarks by the Organizer	Zhou Juxiang, Co-founder and Editor-in-Chief of EETOP
09:30 - 10:10	Chip Computing Power and Computational Circuits	Li Hongge, Responsible Professor and Doctoral Supervisor at Beihang University, and a senior member of the EETOP forum since its early days
10:10 - 10:35	Challenges of Signal Integrity in AI Chip Hardware Design	Jiang Xiuguo, Manager of the SE&CSM Department of the PathWave Design Software Division at Keysight Technologies, and a senior moderator of the Signal Integrity section on the EETOP forum
10:35 - 11:00	Technological Evolution Trends of Post-Silicon Validation	Chen Jiaming, Technical Supervisor of Shanghai Gubo Technology Co., Ltd.
11:00 - 11:25	Advanced Packaging Technologies in the Era of Computing Power	Xu Jian, Packaging Expert at Singular Moore (Shanghai) Integrated Circuit Design Co., Ltd.
11:25 - 11:50	How Chip Engineers Can Optimally Respond to the Next Decade of China's Chip Industry	Hu Yunwang, Partner of Corehui Investment, and senior moderator of sections such as "Job Recruitment and Application", "Career Life", and "Job-hunting Strategies" on the EETOP forum
11:50 - 12:00	Lucky Draw & Summary

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